Espressif Systems /ESP32-S2 /RMT /CH3STATUS

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Interpret as CH3STATUS

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0MEM_WADDR_EX0MEM_RADDR_EX0STATE0 (MEM_OWNER_ERR)MEM_OWNER_ERR 0 (MEM_FULL)MEM_FULL 0 (MEM_EMPTY)MEM_EMPTY 0 (APB_MEM_WR_ERR)APB_MEM_WR_ERR 0 (APB_MEM_RD_ERR)APB_MEM_RD_ERR

Description

Channel 3 status register

Fields

MEM_WADDR_EX

This register records the memory address offset when receiver of CHANNEL%s is using the RAM.

MEM_RADDR_EX

This register records the memory address offset when transmitter of CHANNEL%s is using the RAM.

STATE

This register records the FSM status of CHANNEL%s.

MEM_OWNER_ERR

This status bit will be set when the ownership of memory block is wrong.

MEM_FULL

This status bit will be set if the receiver receives more data than the memory size.

MEM_EMPTY

This status bit will be set when the data to be set is more than memory size and the wraparound mode is disabled.

APB_MEM_WR_ERR

This status bit will be set if the offset address out of memory size when writes via APB bus.

APB_MEM_RD_ERR

This status bit will be set if the offset address out of memory size when reads via APB bus.

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